Implementation of Scalable Montgomery Multiplication Coprocessor in Altera Reconfigurable Hardware

* Technical University of Košice, Department of Electronics and Multimedia Communications, Park Komenského 13, 04120 Košice, Slovak Republic, E-mail: [email protected], Tel: ++421-55-6024169 , Fax: ++421-55-6323989 ** Laboratoire Traitement du Signal et Instrumentation, Unité Mixte de Recherche CNRS 5516, Université Jean Monnet, Saint-Etienne, France, E-mail: [email protected] Abstract – The paper describes implementation of a scalable Montgomery Multiplication (MM) coprocessor in Altera Field Programmable Devices (FPD). Proposed coprocessor performs modular MM with large numbers and can be used as a scalable building block of cryptographic RSA processor. All blocks of the MM coprocessor are implemented in VHDL as parametrized modules and optimized for Altera FPD using large dual port embedded memory blocks. There is no limitation on the maximum size of operands and the selection of actual word-size can be made according to the available FPD capacity and/or desired performance.